/*
 Edge-sensitive sequential UDP test.
*/

module top ;

 wire tq;
 reg ck, data;

 d_edge_ff #(1, 0) flip (tq, ck, data);

 initial begin
  $display ("tq\tflip.q\tclock\tdata\n---------------------------------");
  $strobe  ("%b\t%b\t%b\t%b", tq, flip.q, ck, data);
  data = 1;
  ck = 0;
  #1;
  ck = 1;
  data = 0;
  #1;
  ck = 0;
  #1;
  ck = 1;
  #2;
 end //initial
endmodule

primitive d_edge_ff (q, clock, data);
output q;
reg q;
input clock, data;
table
// clock data   q   q+
   (01)    0  : ? : 0 ;
   (01)    1  : ? : 1 ;
   (0?)    1  : 1 : 1 ;
   (0?)    0  : 0 : 0 ;

   (?0)    ?  : ? : - ;

     ?   (??) : ? : -;
endtable
endprimitive
